/*
 * X1830 cpm definitions
 *
 * Copyright (c) 2017 Ingenic Semiconductor Co.,Ltd
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __X1830_SDRAM_H__
#define __X1830_SDRAM_H__

#define DDRC_STATUS				0x0 /* DDR Status Register */
#define DDRC_CFG				0x4 /* DDR Configure Register */
#define DDRC_CTRL				0x8 /* DDR Control Register */
#define DDRC_LMR				0xc /* DDR Load-Mode-Register */
#define DDRC_REFCNT				0x18 /* DDR  Auto-Refresh Counter */
#define DDRC_MMAP0				0x24 /* DDR Memory Map Config Register */
#define DDRC_MMAP1				0x28 /* DDR Memory Map Config Register */
#define DDRC_DLP				0xbc

#define DDRC_TIMING(n)			(0x60 + 4 * (n - 1)) /* DDR Timing Config Register 1-5 */


#define DDR_APB_OFFSET			(-0x4e0000 + 0x2000)

#define DDRC_PHY_INIT			(DDR_APB_OFFSET + 0x8c)


#define DDR_PHY_OFFSET			(-0x4e0000 + 0x1000)

#define DDRP_CHANNEL_EN			(DDR_PHY_OFFSET + 0x0)
#define DDRP_MEM_CFG			(DDR_PHY_OFFSET + 0x4)
#define DDRP_TRAINING_CTRL		(DDR_PHY_OFFSET + 0x8)
#define DDRP_CL					(DDR_PHY_OFFSET + 0x14)
#define DDRP_AL					(DDR_PHY_OFFSET + 0x18)
#define DDRP_CWL				(DDR_PHY_OFFSET + 0x1c)
#define DDRP_DQ_WIDTH			(DDR_PHY_OFFSET + 0x7c)

#define DDRP_PLL_FBDIV			(DDR_PHY_OFFSET + 0x80)
#define DDRP_PLL_CTRL			(DDR_PHY_OFFSET + 0x84)
#define DDRP_PLL_PDIV			(DDR_PHY_OFFSET + 0x88)

#define DDRP_CALIB_DONE			(DDR_PHY_OFFSET + 0xcc)

/* DDRC Status Register */
#define DDRC_STATUS_ENDIAN		(1 << 7) /* 0 Little data endian
					    1 Big data endian */
#define DDRC_STATUS_MISS		(1 << 6) /* 0 No operation miss DDRC memory mapping
					    1 At least one operation miss DDRC memory mapping */
#define DDRC_STATUS_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
					    1 DDR memory is in deep-power-down state */
#define DDRC_STATUS_PDN			(1 << 4) /* 0 DDR memory is NOT in power-down state
					    1 DDR memory is in power-down state */
#define DDRC_STATUS_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
					    1 DDR memory is in auto-refresh state */
#define DDRC_STATUS_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
					    1 DDR memory is in self-refresh state */
#define DDRC_STATUS_CKE1		(1 << 1) /* 0 CKE1 Pin is low
					    1 CKE1 Pin is high */
#define DDRC_STATUS_CKE0		(1 << 0) /* 0 CKE0 Pin is low
					    1 CKE0 Pin is high */

#endif /* __X1830_SDRAM_H__ */
